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Capacitor voltage ripple minimization in voltage source converter for HVDC applications

Marchesoni, Mario; Passalacqua, Massimiliano; Vaccaro, Luis; Carpita, Mauro; Gavin, Serge; Kissling, Simon
2019
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Title
Capacitor voltage ripple minimization in voltage source converter for HVDC applications
Author(s)
Marchesoni, Mario (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Passalacqua, Massimiliano (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Vaccaro, Luis (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Carpita, Mauro (School of Engineering and Management Vaud, HES-SO, University of Applied Sciences and Arts Western Switzerland)
Gavin, Serge (School of Engineering and Management Vaud, HES-SO, University of Applied Sciences and Arts Western Switzerland)
Kissling, Simon (School of Engineering and Management Vaud, HES-SO, University of Applied Sciences and Arts Western Switzerland)
Date
2019-06
Published in
Proceedings of 2019 AEIT HVDC International Conference (AEIT HVDC), 9-10 May 2019, Florence, Italy
Publisher
Florence, Italy, 9-10 May 2019
Pagination & equivalents
6 p.
Presented at
2019 AEIT HVDC International Conference (AEIT HVDC), Florence, Italy, 2019-05-09, 2019-05-10
ISBN
978-1-7281-2071-3
DOI
https://doi.org/10.1109/AEIT-HVDC.2019.8740647
Keywords
capacitors ; harmonic analysis ; modulation ; legged locomotion ; HVDC transmission ; inverters ; minimization ; HVDC ; MMC ; multilevel converters ; voltage ripple reduction ; efficiency
Paper type
full paper
Faculty
Ingénierie et Architecture
School
HEIG-VD
Institute
iE - Institut des Energies
Note
Cette publication a été rédigée par un membre de l’ancien institut IESE - Institut d'Energie et Systèmes Electriques.
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