Capacitor voltage ripple minimization in voltage source converter for HVDC applications
Marchesoni, Mario; Passalacqua, Massimiliano; Vaccaro, Luis; Carpita, Mauro; Gavin, Serge; Kissling, Simon
2019
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Title Capacitor voltage ripple minimization in voltage source converter for HVDC applications
Author(s) Marchesoni, Mario (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Passalacqua, Massimiliano (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Vaccaro, Luis (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Carpita, Mauro (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland)
Gavin, Serge (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland)
Kissling, Simon (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland)
Date 2019-06
Published in Proceedings of 2019 AEIT HVDC International Conference (AEIT HVDC), 9-10 May 2019, Florence, Italy
Publisher Florence, Italy, 9-10 May 2019
Pagination 6 p.
ISBN 978-1-7281-2071-3
DOI 10.1109/AEIT-HVDC.2019.8740647
Keywords capacitors ; harmonic analysis ; modulation ; legged locomotion ; HVDC transmission ; inverters ; minimization ; HVDC ; MMC ; multilevel converters ; voltage ripple reduction ; efficiency
Conference Type full paper
Faculty Ingénierie et Architecture
School HEIG-VD
Institute IESE - Institut d'Energie et Systèmes Electriques
Record Appears in Conference materials
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