Capacitor voltage ripple minimization in voltage source converter for HVDC applications

Marchesoni, Mario (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Passalacqua, Massimiliano (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Vaccaro, Luis (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy)
Carpita, Mauro (School of Engineering and Management Vaud, HES-SO, University of Applied Sciences and Arts Western Switzerland)
Gavin, Serge (School of Engineering and Management Vaud, HES-SO, University of Applied Sciences and Arts Western Switzerland)
Kissling, Simon (School of Engineering and Management Vaud, HES-SO, University of Applied Sciences and Arts Western Switzerland)

2019-06

Proceedings of 2019 AEIT HVDC International Conference (AEIT HVDC), 9-10 May 2019, Florence, Italy

Florence, Italy, 9-10 May 2019

6 p.

2019 AEIT HVDC International Conference (AEIT HVDC), Florence, Italy, 2019-05-09, 2019-05-10

978-1-7281-2071-3

capacitors ; harmonic analysis ; modulation ; legged locomotion ; HVDC transmission ; inverters ; minimization ; HVDC ; MMC ; multilevel converters ; voltage ripple reduction ; efficiency

full paper

Ingénierie et Architecture

HEIG-VD

iE - Institut des Energies

Cette publication a été rédigée par un membre de l’ancien institut IESE - Institut d'Energie et Systèmes Electriques.

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