Parallel computation has appeared as the most promising technique to circumvent the limitations imposed by power consumption in order to continue increasing computation power, making thus manycore architectures a promising computer organization approach. Interconnecting and coordinating such high amount of computation nodes in an efficient manner is a hot research topic, several approaches to Network-on-chip architectures propose solutions for this. This paper presents a 3D multi-FPGA hardware platform permitting to prototype 3D NoC architectures with dynamic topologies. More precisely, we intend to use it to prototype self-adaptive and self-organizing hardware architectures in which the computation performed by a node and the interconnections between these nodes can be dynamically modified, being these modifications triggered by the platform itself. This paper presents the overall hardware organization and gives some hints about how to use it.