High-Level Synthesis (HLS) is a valuable tool for designing hardware accelerators for post-quantum cryptography (PQC). However, while mapping high-level code to hardware, the quality of the synthesized hardware in terms of latency, power, and area are sensitive to various design parameters and configurations, such as loop unrolling, pipelining, and dataflow optimizations. Previous efforts explored the effects of target frequency on the energy consumption of the generated hardware [1]. In this work, we explore the effects of loop unrolling on the execution time and energy efficiency of the final PQC accelerators. We demonstrate that, despite initial expectations, loop unrolling could worsen the performance and quality of designs in certain circumstances.
