000015331 001__ 15331
000015331 005__ 20250115134147.0
000015331 020__ $$a979-8-3315-3007-5
000015331 0247_ $$2DOI$$a10.1109/FPL64840.2024.00014
000015331 037__ $$aCONFERENCE
000015331 039_9 $$a2025-01-15 13:41:47$$b0$$c2025-01-14 16:19:40$$d1001044$$c2025-01-14 12:00:34$$d0$$y2025-01-14 12:00:17$$z1000099
000015331 041__ $$aeng
000015331 245__ $$aDynaRapid :$$bfast-tracking from C to routed circuits
000015331 260__ $$aPiscataway, NJ, USA$$bInstitute of Electrical and Electronics Engineers
000015331 269__ $$a2024-09
000015331 300__ $$a9 p.
000015331 506__ $$avisible
000015331 520__ $$9eng$$aAdvancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation: while software code compilation may take just a few seconds, FPGA compilation times can often span from several minutes to hours due to the complexity of the underlying toolchain and ever-growing device capacities. In this paper, we present DynaRapid, a fast compilation tool that generates—in a matter of seconds—fully legal placed-and-routed designs for commercial FPGAs. Elastic circuits created by the HLS tool Dynamatic are made exclusively of a limited number of reusable components; we exploit this fact to create a library of placed and routed building blocks, and then stitch together instances of them as needed through RapidWright. Our approach accelerates the C-to-FPGA implementation process by a geomean 20× with only 10% of degradation in operating frequency compared to a conventional commercial off-the-shelf implementation flow.
000015331 540__ $$acorrect
000015331 592__ $$aHEI-VS
000015331 592__ $$bInstitut Systèmes industriels
000015331 592__ $$cIngénierie et Architecture
000015331 6531_ $$9eng$$adegradation
000015331 6531_ $$9eng$$acodes
000015331 6531_ $$9eng$$adesign automation
000015331 6531_ $$9eng$$alaw
000015331 6531_ $$9eng$$acircuits
000015331 6531_ $$9eng$$asoftware
000015331 6531_ $$9eng$$alibraries
000015331 6531_ $$9eng$$alogic
000015331 6531_ $$9eng$$afield programmable gate array
000015331 6531_ $$9eng$$astandards
000015331 655_7 $$apublished full paper
000015331 700__ $$aGuerrieri, Andrea$$uSchool of Engineering, HES-SO Valais-Wallis, HEI, HES-SO University of Applied Sciences and Arts Western Switzerland ; EPFL, Lausanne, Switzerland
000015331 700__ $$aGuha, Srijeet$$uEPFL, Lausanne, Switzerland
000015331 700__ $$aLavin, Chris$$uAMD Research and Advanced Development
000015331 700__ $$aHung, Eddie$$uAMD Research and Advanced Development
000015331 700__ $$aJosipovic, Lana$$uETH Zürich, Zürich, Switzerland
000015331 700__ $$aIenne, Paolo$$uEPFL, Lausanne, Switzerland
000015331 711__ $$a2024 34th International Conference on Field-Programmable Logic and Applications (FPL)$$cTorino, Italy$$d2024-09-02$$m2024-09-06
000015331 773__ $$tProceedings of the 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), 2-6 September 2024, Torino, Italy$$j2024$$q24-32
000015331 8564_ $$uhttps://arodes.hes-so.ch/record/15331/files/Guerrieri_2024_DynaRapid_fast-tracking_C_routed_circuits.pdf$$yPublished version$$94be456e2-c2e0-446d-940c-8e8ac34a2432$$s2738977
000015331 906__ $$aNONE
000015331 909CO $$ooai:hesso.tind.io:15331$$pGLOBAL_SET
000015331 950__ $$aaucun
000015331 980__ $$aconference
000015331 981__ $$aconference