TY  - GEN
AB  - Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation: while software code compilation may take just a few seconds, FPGA compilation times can often span from several minutes to hours due to the complexity of the underlying toolchain and ever-growing device capacities. In this paper, we present DynaRapid, a fast compilation tool that generates—in a matter of seconds—fully legal placed-and-routed designs for commercial FPGAs. Elastic circuits created by the HLS tool Dynamatic are made exclusively of a limited number of reusable components; we exploit this fact to create a library of placed and routed building blocks, and then stitch together instances of them as needed through RapidWright. Our approach accelerates the C-to-FPGA implementation process by a geomean 20× with only 10% of degradation in operating frequency compared to a conventional commercial off-the-shelf implementation flow.
AD  - School of Engineering, HES-SO Valais-Wallis, HEI, HES-SO University of Applied Sciences and Arts Western Switzerland ; EPFL, Lausanne, Switzerland
AD  - EPFL, Lausanne, Switzerland
AD  - AMD Research and Advanced Development
AD  - AMD Research and Advanced Development
AD  - ETH Zürich, Zürich, Switzerland
AD  - EPFL, Lausanne, Switzerland
AU  - Guerrieri, Andrea
AU  - Guha, Srijeet
AU  - Lavin, Chris
AU  - Hung, Eddie
AU  - Josipovic, Lana
AU  - Ienne, Paolo
CY  - Piscataway, NJ, USA
DA  - 2024-09
DO  - 10.1109/FPL64840.2024.00014
DO  - DOI
EP  - 24-32
ID  - 15331
JF  - Proceedings of the 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), 2-6 September 2024, Torino, Italy
KW  - degradation
KW  - codes
KW  - design automation
KW  - law
KW  - circuits
KW  - software
KW  - libraries
KW  - logic
KW  - field programmable gate array
KW  - standards
L1  - https://arodes.hes-so.ch/record/15331/files/Guerrieri_2024_DynaRapid_fast-tracking_C_routed_circuits.pdf
L2  - https://arodes.hes-so.ch/record/15331/files/Guerrieri_2024_DynaRapid_fast-tracking_C_routed_circuits.pdf
L4  - https://arodes.hes-so.ch/record/15331/files/Guerrieri_2024_DynaRapid_fast-tracking_C_routed_circuits.pdf
LA  - eng
LK  - https://arodes.hes-so.ch/record/15331/files/Guerrieri_2024_DynaRapid_fast-tracking_C_routed_circuits.pdf
N2  - Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation: while software code compilation may take just a few seconds, FPGA compilation times can often span from several minutes to hours due to the complexity of the underlying toolchain and ever-growing device capacities. In this paper, we present DynaRapid, a fast compilation tool that generates—in a matter of seconds—fully legal placed-and-routed designs for commercial FPGAs. Elastic circuits created by the HLS tool Dynamatic are made exclusively of a limited number of reusable components; we exploit this fact to create a library of placed and routed building blocks, and then stitch together instances of them as needed through RapidWright. Our approach accelerates the C-to-FPGA implementation process by a geomean 20× with only 10% of degradation in operating frequency compared to a conventional commercial off-the-shelf implementation flow.
PB  - Institute of Electrical and Electronics Engineers
PP  - Piscataway, NJ, USA
PY  - 2024-09
SN  - 979-8-3315-3007-5
SP  - 24-32
T1  - DynaRapid :fast-tracking from C to routed circuits
TI  - DynaRapid :fast-tracking from C to routed circuits
UR  - https://arodes.hes-so.ch/record/15331/files/Guerrieri_2024_DynaRapid_fast-tracking_C_routed_circuits.pdf
VL  - 2024
Y1  - 2024-09
ER  -