@article{Guerrieri:15331,
      recid = {15331},
      author = {Guerrieri, Andrea and Guha, Srijeet and Lavin, Chris and  Hung, Eddie and Josipovic, Lana and Ienne, Paolo},
      title = {DynaRapid : fast-tracking from C to routed circuits},
      publisher = {Institute of Electrical and Electronics Engineers},
      journal = {Proceedings of the 2024 34th International Conference on  Field-Programmable Logic and Applications (FPL), 2-6  September 2024, Torino, Italy},
      address = {Piscataway, NJ, USA. 2024-09},
      number = {CONFERENCE},
      pages = {9 p.},
      abstract = {Advancements in design automation technologies, such as  high-level synthesis (HLS), have raised the input  abstraction level and made the design entry process for  FPGAs more friendly to software programmers. In contrast,  the backend compilation process for implementing designs on  FPGAs is considerably more lengthy compared to software  compilation: while software code compilation may take just  a few seconds, FPGA compilation times can often span from  several minutes to hours due to the complexity of the  underlying toolchain and ever-growing device capacities. In  this paper, we present DynaRapid, a fast compilation tool  that generates—in a matter of seconds—fully legal  placed-and-routed designs for commercial FPGAs. Elastic  circuits created by the HLS tool Dynamatic are made  exclusively of a limited number of reusable components; we  exploit this fact to create a library of placed and routed  building blocks, and then stitch together instances of them  as needed through RapidWright. Our approach accelerates the  C-to-FPGA implementation process by a geomean 20× with only  10% of degradation in operating frequency compared to a  conventional commercial off-the-shelf implementation flow.},
      url = {http://arodes.hes-so.ch/record/15331},
      doi = {https://doi.org/10.1109/FPL64840.2024.00014},
}