000015328 001__ 15328
000015328 005__ 20250115134147.0
000015328 020__ $$a979-8-3315-3007-5
000015328 0247_ $$2DOI$$a10.1109/FPL64840.2024.00025
000015328 037__ $$aCONFERENCE
000015328 039_9 $$a2025-01-15 13:41:47$$b0$$c2025-01-14 16:11:31$$d1001044$$c2025-01-14 09:40:11$$d0$$y2025-01-14 09:40:02$$z1000099
000015328 041__ $$aeng
000015328 245__ $$aFast switching activity estimation for HLS-produced dataflow circuits
000015328 260__ $$aPiscataway, NJ, USA$$bInstitute of Electrical and Electronics Engineers (IEEE)
000015328 269__ $$a2024-09
000015328 300__ $$a8 p.
000015328 506__ $$avisible
000015328 520__ $$9eng$$aHigh-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction level they operate on typically contains no or limited information on low-level circuit details that power consumption depends on. Dataflow circuits have recently been explored in the HLS context; apart from their ability to achieve performance that is superior to standard HLS-generated circuits, their well-defined structure and computational model offer entirely new opportunities for reasoning about power at the HLS level. This paper exploits this insight to present an accurate switching activity estimator for HLS-produced dataflow circuits. Our estimator combines the knowledge about the dataflow circuit structure with software profiling and detailed glitching analysis to estimate the circuit’s switching activity with an average error rate of 1.8% and average speedup of 17.8× compared with a cycle-accurate simulator. Our technology-agnostic solution makes a critical advancement in HLS power estimation and sets the stage for integrating power optimization within the HLS process.
000015328 540__ $$aincorrect
000015328 592__ $$aHEI-VS
000015328 592__ $$bInstitut Systèmes industriels
000015328 592__ $$cIngénierie et Architecture
000015328 6531_ $$9eng$$aswitching activity
000015328 6531_ $$9eng$$apower estimation
000015328 6531_ $$9eng$$ahigh-level synthesis
000015328 6531_ $$9eng$$adataflow circuits
000015328 655_7 $$apublished full paper
000015328 700__ $$aLiu, Jiantao$$uETH Zürich, Zürich, Switzerland
000015328 700__ $$aGraczyk, Maksymilian$$uETH Zürich, Zürich, Switzerland
000015328 700__ $$aGuerrieri, Andrea$$uEPFL, Lausanne, Switzerland ; School of Engineering, HES-SO Valais-Wallis, HEI, HES-SO University of Applied Sciences and Arts Western Switzerland
000015328 700__ $$aJospipovic, Lana$$uETH Zürich, Zürich, switzerland
000015328 711__ $$a2024 34th International Conference on Field-Programmable Logic and Applications (FPL)$$cTorino, Italy$$d2024-09-02$$m2024-09-06
000015328 773__ $$tProceedings of the 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), 2-6 September 2024, Torino, Italy$$j2024$$q118-125
000015328 8564_ $$uhttps://arodes.hes-so.ch/record/15328/files/Guerrieri_2024_fast_switching_activity_estimation_HLS-produced_dataflow_circuits.pdf$$yPublished version$$940df3697-a0c8-47bc-a5c9-0916858644b5$$s713731
000015328 906__ $$aNONE
000015328 909CO $$ooai:hesso.tind.io:15328$$pGLOBAL_SET
000015328 950__ $$aaucun
000015328 980__ $$aconference
000015328 981__ $$aconference