@article{Liu:15328,
      recid = {15328},
      author = {Liu, Jiantao and Graczyk, Maksymilian and Guerrieri,  Andrea and Jospipovic, Lana},
      title = {Fast switching activity estimation for HLS-produced  dataflow circuits},
      publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
      journal = {Proceedings of the 2024 34th International Conference on  Field-Programmable Logic and Applications (FPL), 2-6  September 2024, Torino, Italy},
      address = {Piscataway, NJ, USA. 2024-09},
      number = {CONFERENCE},
      pages = {8 p.},
      abstract = {High-level synthesis (HLS) tools generate hardware designs  from high-level software languages while sidestepping  intricate low-level hardware details. However, HLS tools  struggle with precise dynamic power estimation and  optimization: the high abstraction level they operate on  typically contains no or limited information on low-level  circuit details that power consumption depends on. Dataflow  circuits have recently been explored in the HLS context;  apart from their ability to achieve performance that is  superior to standard HLS-generated circuits, their  well-defined structure and computational model offer  entirely new opportunities for reasoning about power at the  HLS level. This paper exploits this insight to present an  accurate switching activity estimator for HLS-produced  dataflow circuits. Our estimator combines the knowledge  about the dataflow circuit structure with software  profiling and detailed glitching analysis to estimate the  circuit’s switching activity with an average error rate of  1.8% and average speedup of 17.8× compared with a  cycle-accurate simulator. Our technology-agnostic solution  makes a critical advancement in HLS power estimation and  sets the stage for integrating power optimization within  the HLS process.},
      url = {http://arodes.hes-so.ch/record/15328},
      doi = {https://doi.org/10.1109/FPL64840.2024.00025},
}