Intermediate address space : virtual memory optimization of heterogeneous architectures for cache-resident workloads

Intermediate address space : virtual memory optimization of heterogeneous architectures for cache-resident workloads

LIu, Qunyou (EPFL, Lausanne, Switzerland)
Huang, Darong (EPFL, Lausanne, Switzerland)
Costero, Luis (Universidad Complutense de Madrid (UCM), Madrid, Spain)
Zapater, Marina (School of Engineering and Management Vaud, HES-SO University of Applied Sciences and Arts Western Switzerland ; EPFL, Lausanne, Swizerland)
Atienza, David (EPFL, Lausanne, Switzerland)

2024-04

ACM Transactions on Architecture and Code Optimization

2024, 21

3

n°50, p. 1-23

New York, USA, ACM

22 p.

1544-3566

software and its engineering ; virtual memory ; computer systems organization ; multicore architectures ; computer architecture ; CPU ; GPU ; TLB ; cache

scientifique

Ingénierie et Architecture

HEIG-VD

ReDS - Reconfigurable & embedded Digital Systems

Articles scientifiques
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