This paper presents the comparison of two design methodologies applied to the design of a co-processor dedicated to image processing. The first methodology is the classical development based on specifying the architecture by directly writing a HDL model using VHDL or Verilog. The second methodology is based on specifying the architecture by using a high level dataflow language followed then by direct synthesis to HDL. The priciple of developing a dataflow description consists on defining a network of autonomous entities called actors, which can communicate only by sending and receiving data tokens. Each entity in the process of consuming and generating data tokens performs completely independent and concurrent processing. A heterogeneous platform composed by a SW processor and the designed HW co-processor is used to compare the results of the designs obtained by the two different methodologies. The comparison of the results shows that the implementations based on the dataflow methodology, not only can be completed with an important reduction of design and development time, but also enable efficient re-design iterations capable of achieving performances, which are comparable in efficiency to design obtained by hand written HDL.